Radboud Digital Security group Lunch Talk homepage

Welcome to the site of the talks organised by Radboud Digital Security group. We organize a talk every Wednesday at 12:30.

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Upcoming talks

  • Wednesday, 12th of March 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Durba Chatterjee

    I know what your compiler did: Optimization Effects on Power Side-Channel Leakage for RISC-V

    With the rapid growth of software-based cryptographic implementations, particularly in high-level languages, understanding the role of architectural and micro-architectural components in side-channel security has become paramount.
    While micro-architectural factors introduce target-specific leakage, architectural leakage is significantly influenced by compiler optimizations.
    The impact of compiler optimizations on power-based side-channel leakage remains largely unexplored due to challenges in isolating the architectural power component.
    In this talk, we explore the effects of compiler optimizations on power-based side-channel leakage in RISC-V architectures and propose ARCHER, an architecture-level tool for side-channel analysis and root cause identification of cryptographic software on RISC-V processors supporting pre-silicon analysis of high-level and assembly code.
    Using ARCHER, we analyze binary transformations across five optimization levels (-O0, -O1, -O2, -O3, -Os) of the GCC compiler for unprotected and masked AES implementations, providing insights into how varying optimization levels affect power-based side-channel leakage.
    We identify a compiler-induced vulnerability in ShiftRows operation of masked AES using correlation analysis on simulated traces.
    We validate our findings using power traces from an ASIC implementation of the PicoRV32 core, confirming that compiler-induced vulnerabilities manifest in real power traces.
    We introduce two dataflow metrics for predicting side-channel leakage based on binary transformations to enhance practical applicability.
    These metrics, coupled with the analysis and visualization capabilities of ARCHER, provide designers with effective tools to assess and mitigate power-based side-channel vulnerabilities at the software optimization stage, advancing the security of cryptographic implementations in resource-constrained environments.

  • Friday, 21st of March 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Rob Romijnders

    TBA

  • Wednesday, 26th of March 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Zahra Moti

    TBA

  • Wednesday, 2nd of April 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Jan den Besten

    TBA

  • Wednesday, 9th of April 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    Dis Lunch by Lilika Markatou

    TBA

  • Friday, 11th of April 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Sengim Karayalcin

    It's Not Just a Phase: On Investigating Phase Transitions in Deep Learning-based Side-channel Analysis

    Side-channel analysis (SCA) represents a realistic threat where the attacker can observe unintentional information to obtain secret data.
    Evaluation labs also use the same SCA techniques in the security certification process.
    The results in the last decade have shown that machine learning, especially deep learning, is an extremely powerful SCA approach, allowing the breaking of protected devices while achieving optimal attack performance.
    Unfortunately, deep learning operates as a black-box, making it less useful for security evaluators who must understand how attacks work to prevent them in the future.
    This work demonstrates that mechanistic interpretability can effectively scale to realistic scenarios where relevant information is sparse and well-defined interchange interventions to the input are impossible due to side-channel protections.
    Concretely, we reverse engineer the features the network learns during phase transitions, eventually retrieving secret masks, allowing us to move from black-box to white-box evaluation.

  • Wednesday, 16th of April 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Matteo Gioele Collu

    TBA

  • Wednesday, 23rd of April 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Tom Meurs and Raphael Hoheisel (Politie Oost)

    TBA

  • Wednesday, 30th of April 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Luqman Zagi

    TBA

  • Wednesday, 7th of May 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by TBA

    TBA

  • Wednesday, 14th of May 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by TBA

    TBA

  • Wednesday, 21st of May 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by Vianney Lapotre

    TBA

  • Wednesday, 28th of May 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by TBA

    TBA

  • Wednesday, 4th of June 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by TBA

    TBA

  • Wednesday, 11th of June 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by TBA

    TBA

  • Wednesday, 18th of June 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by TBA

    TBA

  • Wednesday, 25th of June 2025 at 12:30 in the big lecture room in Mercator 1 (MERC1_00.28, ground floor)
    DiS Lunch by TBA

    TBA

  • Past talks